This patent application claims priority based on a Japanese patent application, H11-192627 filed on Jul. 7, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a memory testing apparatus for testing memory devices, and it particularly relates to the memory testing device capable of performing failure analysis on the memory devices.
2. Description of the Related Art
In recent years, high integration of the memory devices has been significant due to developments in semiconductor manufacturing processes. Thus, there are many occasions where large-scale newly developed memory needs to be tested. Evaluating a whole memory devices as a failure as a result of a single failure cell (defective spot) in the memory device is not ideal in terms of productivity or yield.
Thus, there is available a method in which the memory device is equipped with a redundant structure in advance, so that a failure cell can be saved by replacing the failure cell with a spare memory. In this method, a memory device which is non-defective as a whole can be produced even though part of cell is defective, so that the yield can be improved. Moreover, a defective spot can be scrutinized so as to perform the failure analysis for finding and mending a cause of the failure, thus being desirable in the course of improving the yield of the devices.
FIG. 1 shows how a pattern generator 10 is connected to a failure memory 20 in the conventional memory testing apparatus, which tests a memory under test. The pattern generator 10 includes a sequence control unit 12; an address generator 14; a data generator 16; and a control signal generator 18. The address generator 14 includes: an internal address generator 26; an address converting unit 28; and selectors 30a and 30b. Moreover, the failure analysis memory 20 includes: a defective data storing memory 22; and a failure history storing memory 24. The defective data storing memory has the same capacity as that of the memory device under test.
The sequence control unit 12 generates a sequence signal 32 that controls the sequence of the address generator 14, data generator 16 and control signal generator 18. In the address generator 14, the internal address generator 26 generates an internal address corresponding to the cell configuration of the memory under test, based on the sequence control signal 32. Here, the memory cell of the memory device is configured in the optimum position, so that an address to be input to the address pin of the memory device is not necessarily matched up with the internal address within the cell. This is because the wiring, which connects the address pin to each cell, is formed by a request concerning the physical configuration and arrangement. Thus, the address converting unit 28 converts the internal address to an input address which specifies the cell of the memory under test that the internal address primarily addresses, from the address pin of the memory under test. The internal address corresponds to the input address in a one-to-one manner. The selector 30a selects the input address and outputs the input address signal 34 to the memory under test. The input address signal 34 that is input to the memory under test accesses a memory cell specified by the corresponding internal address.
When a defective spot is found in the memory under test as a result of the test, the pattern generator 10 supplies to the failure analysis memory 20 the data on defective saving and/or failure analysis. The selector 30b supplies an address signal 36 which corresponds to the address of the defective spot of the memory under test, to the address pin of the defective data storing memory 22 and the data pin of the failure history storing memory 24. The address signal 37 is either the internal address signal corresponding to the internal cell of the memory under test, or the input address in which the internal address signal is converted based on the physical configuration and arrangement of the internal cell of the memory under test and the address pins. Moreover, the data generator 16 supplies to the data pin of the failure history storing memory 24, a data signal 38 acquired at the time the detective spot was detected. At the same time, the control signal generator 18 supplies to the data pin of the failure history storing memory 24, a control signal 40 acquired at the time of detection of the defective spot. The defective data is supplied to the data pin of the failure data storing memory 22 while an increment signal is supplied to the address pin of the failure history storing memory 24.
As a result thereof, in the defective data storing memory 22, the defective data is written to an address corresponding to an address cell of the defective cell of the memory under test. Moreover, in the failure history storing memory 24, the failure history data such as data and address at the time of testing are written thereto in the order that the failures were detected. Data stored in the defective data storing memory 22 and the failure history storing memory 24 will be utilized in saving the defective cells as well as in failure analysis at a later stage.
Since in the conventional memory testing apparatus there exists only a single signal transmission line system between the pattern generator 10 and each of the defective data storing memory 22 and the failure history storing memory 24, the pattern generator 10 can only supply either the internal address or the input address signal to the defective data storing memory 22 and the failure history storing memory 24.
Thus, in the event that there is a request for supplying the internal address to the defective data storing memory 22 and for supplying the input address signal to the failure history storing memory 24, two steps of operations must be taken in the conventional memory testing apparatus. Namely, in satisfying this request, first the internal address signal indicating the defective address is stored in the defective data storing memory 22, and it is further required that, next, a program for the test is changed, so that the input address corresponding to the defective address is supplied to the failure history storing memory 24.
In that case, the test must be carried out at least twice, in order to store the data for use in the failure analysis, to the failure analysis memory 20. There is a problem in that development cost increases and hence a device will cost more, if it takes a longer time to perform the failure analysis. In this manner, it remains an important subject matter in the conventional practice, that data transmission time from the pattern generator 10 to the failure analysis memory 20 shall be shortened as much as possible.
Therefore, it is an object of the present invention to provide a memory testing apparatus which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to an aspect of the present invention, a memory testing apparatus for testing a memory, comprises: a pattern generator which outputs: an input address signal supplied to an address pin of the memory, an input test signal, including an input data signal, supplied to a data pin of the memory, and an expectation value data signal which is an expectation value data signal that is to be output, based on the input test signal, from the memory, as a response result from a normal memory device; a signal input-output unit which supplies the input test signal to the memory and receives an output data signal from the memory; a comparator which compares the output data signal with the expectation value data and outputs a defect-indicating data indicative of existence of a defective spot in the memory; a defective data storing memory which writes the defect-indicating data output from the comparator, to an address corresponding to the defective spot of the memory; and a failure history storing memory which stores failure history data including the input data signal when the defective spot is detected, wherein the pattern generator includes: an internal address generator which generates an internal address signal specifying an address based on a cell configuration inside the memory; an address converting unit which, based on a correspondence relationship between the cell configuration inside the memory and a pin configuration of the address pin, converts the internal address to the input address signal that is to be input to the address pin; a first address output unit which outputs to the defective data storing memory either the internal address signal or the input address signal; and a second address output unit which outputs to the failure history storing memory either the internal address signal or the input address signal.
The second address output unit outputs to the failure history storing memory either the internal address signal or the input address signal in a manner corresponding to the input data signal.
Preferably, the internal address signal represents a logical address and the input address signal represents a physical address.
Moreover, an input of the second address output unit may be connected to the first address output unit.
According to different aspect of the present invention, a memory testing apparatus for testing a memory, comprises: a pattern generator which outputs: an input address signal supplied to an address pin of the memory, an input test signal, including an input data signal, supplied to a data pin of the memory, and an expectation value data signal which is an expectation value data signal that is to be output, based on the input test signal, from the memory, as a response result from a normal memory device; a signal input-output unit which supplies the input test signal to the memory and receives an output data signal from the memory; a comparator which compares the output data signal with the expectation value data and outputs a defect-indicating data indicative of existence of a defective spot in the memory; a defective data storing memory which writes the defect-indicating data output from the comparator, to an address corresponding to the defective spot of the memory; and a failure history storing memory which stores failure history data including the input data signal when the defective spot is detected, wherein the pattern generator includes: a sequence control unit which generates a sequence control signal that controls an address generator, a data generator and a control signal generator connected thereto, where the address generator outputs a first address signal and a second address signal therefrom, and the address generator is connected, via two separate transmission lines, respectively to the defective data storing memory and the failure history storing memory, whereby the first address signal and the second address signal can be independently and separately supplied to the defective data storing unit and the failure history storing memory, respectively.
The address generator preferably comprises: an internal address generator which generates an internal address signal that specifies an address based on a cell configuration inside the memory; an address converting unit which converts the internal address signal to the input address signal; a first address output unit which outputs to the defective data storing memory a first address signal that is either the internal address signal or the input address signal; and a second address output unit which outputs to the failure history storing memory a second address signal that is either the internal address signal or the input address signal.
The address generator may further comprise: an address output unit which constantly supplies the input address signal to the memory.
Preferably, second address output unit 124 outputs the second address signal to the failure history storing memory in a manner corresponding to the input data signal and the control signal when the defective spot is detected.
Moreover, the first address output unit and the second address output unit may be multiplexers, so as to be able to select one among the internal address signal and the input address signal.
According to an other aspect of the present invention, a method for testing a memory, comprises steps of: generating an internal address signal specifying an address based on a cell configuration inside the memory; converting the internal address signal to an input address signal; supplying to the memory the thus converted input address signal and a input test signal including an input data signal that is to be input to a data pin of the memory; generating an expectation value data signal which is to be output, based on the input test signal, from the memory, as a response result from a normal memory device; detecting a defective spot of the memory by comparing the output data signal output from the memory and the expectation value data signal; and outputting to a defective data storing memory both a defective-indicating data indicating of existence of the defective spot in the memory and the internal address signal, and simultaneously outputting to a failure history storing memory both failure history data including the input data signal when the defective spot is detected, and the input address signal.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.